1. Field of the Invention
The present invention relates to monolithic power semiconductor devices and more particularly to the optimization of lateral components in such power semiconductor devices.
2. Discussion of the Related Art
Generally, semiconductor devices, designed to conduct high currents and to withstand high voltages, are vertically disposed on silicon wafers. A specific example is illustrated in FIG. 1 which is a schematic cross-sectional view of a thyristor. The component is fabricated from a silicon wafer having a thickness ranging from 0.2 mm to 0.4 mm and made of a very low doped single-crystal semiconductor (usually 1014 to 1016 atoms/cm3). A main electrode of the thyristor is formed on the upper or front surface of the wafer and the other main electrode is formed on the lower surface. In the represented example, substrate N1 corresponds to an N-type silicon wafer. The lower surface, or back surface, has a P-type diffusion P2 and, in the front surface, is formed a P-type region P3 in which an N-type region N4 is diffused. A cathode metallization K contacts region N4 and a gate metallization G contacts region P3. The remaining thickness of the substrate N1 between its interfaces with regions P2 and P3 determines, in particular, the breakdown voltage of the component. In this type of vertical structure, insulation walls 3 and 4 respectively formed from the upper and lower surfaces and contacting each other to delineate a portion of substrate N1, are frequently provided.
A plurality of types of vertical power components are known, for example thyristors, triacs, power transistors, power MOS transistors and various alternatives of these components with a direct or indirect control and possibly with a voltage-control (control through MOS transistor). Generally, all these components are characterized by a vertical structure, along the thickness of a wafer, and by the fact that at least one of their constitutive layers corresponds to a thick portion of the low doped substrate. In addition, over the last years, numerous improvements have been achieved for doping the back surfaces of wafers and various diffusions are commonly formed in the back surface. It is also known that a portion of the back surface can be insulated from the back surface metallization.
In some cases, it is further desired to form lateral components in power devices.
FIG. 2 represents an example of such a component, which is a PNP transistor formed in the upper or front surface of substrate N1 and including a P-type emitter region P5, a P-type collector region P6 and an N-type base contact region N7. As for a vertical component, if it is desired that the breakdown voltage of this component be high, the lateral space between regions P5 and P6 should be large, substantially equal to the vertical thickness of layer N1 represented in FIG. 1.
FIG. 3 represents an exemplary lateral transistor formed in the upper surface of substrate N1 and including a P-type anode region P10, a P-type cathode-gate region P and an N-type cathode region N12 which is formed in region P11. A region N13 has a stop-channel function. Here again, if it is desired that the breakdown voltage be high, the lateral space between regions P10 and P11 should be large, substantially equal to the vertical thickness of layer N1 represented in FIG. 1.
Generally, it is desired to provide transistors with a relatively high gain and/or relatively sensitive lateral thyristors, i.e., the transistors which form the thyristors should have a relatively high gain. This is a priori difficult because of the large distance between the P regions necessary to obtain a high breakdown voltage. In order to increase the gain, the doping and the deepness of regions P5, P6, P10 and P11, as well as the location of the various regions (ring or digited structures) are optimized. However, it is difficult to obtain satisfying solutions and, even when possible, this requires fabrication of some layers with specific doping levels and patterns, which causes that these layers can no longer be realized at the same time as other layers fabricated in the same semiconductor device for other components of the device.
Another lateral component is represented in FIG. 4A and corresponds to the series connection of two diodes, as represented in FIG. 4B, which are formed on the front side of a substrate N1. The first diode is formed by the junction between a P-type region P20 and an N-type region N21 formed in region P20. The first diode includes a metallization A1 contacting region N21 and a metallization B1 contacting region P20, generally with interposition of a highly doped P-type region P22. Likewise, the second diode includes a region P24, a region N25 and a region P26 which are arranged as represented in FIG. 4A. Region N25 contacts the same metallization B1 as region P22 and region P26 contacts metallization C1.
FIGS. 5A and 5B are identical to FIGS. 4A and 4B with the difference that, in FIG. 5A, the device is formed from a P-type substrate instead of an N-type substrate.
A drawback of the structures of FIGS. 4A and 5A is that parasitic thyristors may be triggered, such as the thyristor formed by regions N21-P20-N1-P24 or other parasitic thyristors liable to exist between various series of diodes formed in the same substrate, for example to form a monolithic rectifying bridge. In this case, in contrast to the case represented in FIG. 3, it is desired to reduce as much as possible the sensitivity of the parasitic thyristors, i.e., the gain of the bipolar transistors which form the thyristors. Metal diffusions (gold, platinum) or electron or proton irradiations are used. However, this increases the complexity of the fabrication process; in addition, the effects of such processes are difficult to accurately localize.
All the known methods to adjust the sensitivity or the gain have, as indicated above, the drawback of not optimally providing the desired result, and the drawback of requiring additional fabrication steps with respect to the usual fabrication steps of a power semiconductor device.
An object of the present invention is to optimize the gain or sensitivity of desired or parasitic lateral components to be able to select a high gain in the case of desired components or a low gain in the case of parasitic components without the need for other fabrication steps than those currently used to fabricate a power semiconductor device.
To achieve this and other objects, the present invention provides a method for adjusting the gain or the sensitivity of a lateral component formed in the upper surface of a semiconductor wafer of a first conductivity type, including the steps of not doping or highly doping according to the first conductivity type, the back surface when it is desired to reduce the gain or sensitivity of the lateral component, and doping according to the second conductivity type, the back surface when it is desired to increase the gain or the sensitivity of the lateral component.
According to an embodiment of the present invention, the diffusion of the first conductivity type of the back surface is increased with the desired decrease of the gain.
According to an embodiment of the present invention, the diffusion of the second conductivity type of the back surface is increased with the desired increase of the gain.
The present invention also achieves a lateral transistor or thyristor formed in the front surface of a low doped semiconductor wafer of a first conductivity type including on the back surface of the wafer a layer of the second conductivity type.
According to an embodiment of the present invention, the layer of the second conductivity type extends substantially through one half of the substrate thickness and is formed at the same time as lateral diffusion walls formed from the back surface.
The present invention also achieves a set of PN junction diodes formed on the front surface of a low doped semiconductor wafer of a first conductivity type, in which the back surface of the substrate includes a highly doped region of the first conductivity type.